A plasma screen is an array-type screen, formed of cells disposed at the intersections of lines and columns. A cell includes a cavity filled with a rare gas, two control electrodes and a red, green, or blue phosphor deposition. To create a light spot on the screen, by using a given cell, a potential difference is applied between the control electrodes of the cell, to trigger an ionization of its gas. This ionization goes with an emission of ultraviolet rays. The creation of the light spot is obtained by excitation of the deposited phosphor, by the emitted rays.
The cell control, to create images, is conventionally performed by logic circuits generating control signals. The logic states of these signals determine the cells which are controlled to generate a light spot and those which are controlled not to generate one. These logic circuits are generally supplied at low voltage, for example, with a supply voltage of 5 volts or less. This voltage is not sufficient to directly drive the cell electrodes. Between the logic circuits and the cells to be controlled, power output stages are thus used, to convert the low voltage control signals into high voltage control signals.
The ionization of the gas in the cavities requires the application of high potentials on the control electrodes, on the order of magnitude of one hundred volts. On the other hand, it is necessary to be able to provide the electrodes with (and, correlatively, to receive from these electrodes) significant currents, on the order of several tens of milliamperes. Indeed, the electrodes can be represented, schematically, by relatively high equivalent capacitances on the order of one hundred picofarads (and, correlatively, by current sources of some tens of milliamperes). The control of these electrodes is thus equivalent to the charge or discharge control of a capacitor. Now, it is desired, generally, in plasma screens, to obtain signals which have steep edges. This represents, for example, charge and discharge durations on the order of one hundred nanoseconds. Given the high potential to be reached and the high value of the capacitive load, this requires the ability of supplying and absorbing very high charge and discharge currents, which can reach one hundred milliamperes.
As mentioned, the control of the plasma screen electrodes is performed by power output stages receiving low voltage logic signals and converting these signals into high voltage control signals.
FIG. 1 illustrates a conventional example of embodiment of an output stage 1 enabling to control an electrode. Stage 1 includes a control input 2 and an output 4. Control input 2 receives a logic input signal IN1. It is assumed that this signal is a low voltage signal, which can take two states, a high state and a low state. The high state will be represented by a positive potential VCC, with for example VCC=5 V. The low state will be represented by a ground potential GND=0 V. Output 4 supplies an output control signal OUT1. This output signal is issued to an electrode, represented by an equivalent capacitor Cout mounted between output 4 and the ground. The electrode control consists of charging capacitor Cout, bringing it to a high voltage potential VPP, or discharging it, if charged. It will be assumed that the charge is ordered when signal IN1 is in the high state, and that the discharged is ordered when signal IN1 is in the low state.
Stage 1 includes a pair 6 of power transistors 8 and 10. These transistors are, typically, complementary VDMOS-type N-channel and thick oxide HVMOS-type P-channel power transistors. VDMOS refers to vertical N-channel MOS-type transistors, able to withstand high source-drain potential differences and issue or absorb significant currents. Thick oxide HVMOS refers to MOS-type P-channel transistors able to withstand high source-drain and source-gate potential differences. Transistor 8, of P-channel HVMOS type, receives potential VPP on its source. Its drain is connected to output 4 and its control gate receives a control signal INP. This transistor enables to charge capacitor Cout, when on. Transistor 10 then is off. Transistor 10, of N-channel VDMOS type, receives potential GND on its source. Its drain is connected to output 4 and its control gate receives a control signal INN. This transistor enables to discharge capacitor Cout, when on. Transistor 8 is then off. The control of discharge transistor 10 is implementable at low voltage. When INN=VCC, it is on, and when INN =GND, it is off. Thus, in circuit 1, signal INN is issued by an inverter 12 receiving signal IN1. A low voltage inverter will be used, powered by potentials VCC and GND. This inverter enables to invert the polarity of signal IN1 so that the charge and the discharge be controlled, respectively, by IN1=VCC and IN1=GND. The control of charge transistor 8 requires a high voltage control. Indeed, when INP=GND, transistor 8 is on, but to turn it off, signal INP has to be able to reach a potential at least equal to VPP. For this purpose, the control of transistor 8 is performed by a potential shifting circuit 14, circuit 14 being driven by input signal IN1.
Circuit 14 includes two MOS-type P-channel power transistors 16 and 18, and two N-channel MOS-type power transistors 20 and 22. Transistors able to withstand the high voltage will be used, for example, N-channel VDMOS transistors and thick oxide P-channel HVMOS transistors. Transistors 16 and 18 receive potential VPP on their sources. Transistors 20 and 22 receive potential GND on their sources. The drain of transistor 16 is connected to the control gate of transistor 18 and to the drain of transistor 20. The drain of transistor 18 is connected to the control gate of transistor 16 and to the drain of transistor 22. The drains of transistors 18 and 22 issue control signal INP. Transistor 20 receives signal INN on its control gate. Eventually, transistor 22 receives a control signal NIN on its control gate. This signal NIN is issued by an inverter 24, powered at low voltage, and receiving signal INN as an input. When INN=GND, transistors 20 and 22 are, respectively, off and on. Transistors 16 and 18 are, therefore, respectively on and off. Then, INP=GND. Charge transistor 8 is on and discharge transistor 10 is off. When INN=VCC, then transistors 20 and 22 are, respectively, on and off. Transistors 16 and 18 are, therefore, respectively off and on. Then, INP=VPP. Charge transistor 8 remains off and discharge transistor 10 is on.
A first problem raised by the circuit of FIG. 1 is the surface required to implement charge transistor 8. Indeed, given, on the one hand, the differences of conductivity of the P-channel and N-channel transistors and, on the other hand, the high values of the charge and discharge currents, transistor 8 occupies a surface on the order of two or three times as much as that occupied by transistor 10, with an equivalent current performance.
A second problem raised by the circuit of FIG. 1 is the risk of simultaneous conduction of output transistors 8 and 10, when input signal IN1 changes states. Such simultaneous conduction, when the control signals of transistors 8 and 10 are modified, causes a high dissipation, given the voltage and current values concerning these transistors.